I read an article recently where an Engineer had designed a timing circuit, but when it was tested, the frequency was too high. The engineer rechecked all of the calculations and found out from the capacitor datasheet that the value of the particular multilayer ceramic capacitor that was chosen, changes with the applied voltage.

I did not pay much attention to it, being more involved with power supplies, until I was talking with one of our TDK-Lambda Engineers regarding non-isolated POL (Point of Load) converters, and he gave me the same warning about the value selection of the filter capacitors. This is covered in the ceramic capacitor datasheets under DC Bias characteristics.

POL converters rely on quite large ceramic capacitors on the input and output to reduce the effect of the fast transient currents drawn by FPGAs, (which can cause the output voltage to deviate), with values sometimes approaching 2,000 uF.

The concern our Engineer had was that our customers might not know about this. Intrigued I decided to investigate. Below is the DC-Bias Characteristic for a 22 uF 16V multilayer ceramic capacitor.

If a capacitor value of 22 uF was recommended by the application note for filtering the 12V input voltage on a non-isolated converter and the user picked this particular part, in actuality, the real capacitance would be closer to 12 uF.

Upon testing the filtering, the user might complain that the application note was incorrect, whereas in fact the capacitor datasheet had not been interpreted correctly.

Something to bear in mind!